ISSN 0253-2778

CN 34-1054/N

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A multiprocessor architecture supporting dynamic partial reconfiguration

  • 1.

    School of Computer Science and Technology, USTC, Hefei 230027, China

  • 2.

    Embedded System Lab, Suzhou Institution for Advanced Study, USTC, Suzhou 215123, China

Cite this:
https://doi.org/10.3969/j.issn.0253-2778.2014.04.008
  • Received Date: 18 March 2013
  • Accepted Date: 16 July 2013
  • Rev Recd Date: 16 July 2013
  • Publish Date: 30 April 2014
    Abstract

  • Abstract

    The intrinsic characteristics of embedded applications such as diversity and variability, together with their stringent requirements for computing performance, impose significant challenges on embedded system design. By providing a hardware/software co-design flow, an underlying communication interface, a parallel programming model and the relevant runtime environment, dynamic partial reconfigurable computing (DPR) technology was presented for service-oriented multiprocessor (SOMP) system. The DPR technology can effectively improve the system flexibility without performance loss, enabling the system to satisfy the requirements of more diverse embedded applications. An SOMP prototyping system has been implemented on the development board for the Xilinx Virtex-5 FPGA. A series of experiments were conducted and the results demonstrate the correctness and the resulting flexibility of the proposed architecture.

    Abstract

    The intrinsic characteristics of embedded applications such as diversity and variability, together with their stringent requirements for computing performance, impose significant challenges on embedded system design. By providing a hardware/software co-design flow, an underlying communication interface, a parallel programming model and the relevant runtime environment, dynamic partial reconfigurable computing (DPR) technology was presented for service-oriented multiprocessor (SOMP) system. The DPR technology can effectively improve the system flexibility without performance loss, enabling the system to satisfy the requirements of more diverse embedded applications. An SOMP prototyping system has been implemented on the development board for the Xilinx Virtex-5 FPGA. A series of experiments were conducted and the results demonstrate the correctness and the resulting flexibility of the proposed architecture.
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    • References(17)
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    Wolf W, Jerraya A A, Martin G. Multiprocessor system-on-chip technology[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2008, 27(10):1 701-1 713.
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    Compton K, Hauck S. Reconfigurable computing: A survey of systems and software[J]. ACM Computing Surveys, 2002, 34(2): 171-210.
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    Zynq-7000 All Programmable SoC[EB/OL]. http://www.xilinx.com/.
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    Watkins M A, Albonesi D H. ReMAP: A reconfigurable heterogeneous multicore architecture[C]// 43rd Annual IEEE/ACM International Symposium on Microarchitecture. Atlanta, USA: IEEE Press, 2010: 497-508.
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    Kahle J A, Day M N, Hofstee H P, et al. Introduction to the Cell multiprocessor[J]. IBM Journal of Research and Development, 2005, 49(4/5): 589-604.
    [7]
    DeHon H, Markovsky Y, Caspi E, et al. Stream computations organized for reconfigurable execution[J]. Microprocessors and Microsystems, 2006, 30(6): 334-354.
    [8]
    Chamberlain R D, Franklin M A, Tyson E J, et al. Auto-pipe: Streaming applications on architecturally diverse systems[J]. Computer, 2010, 43(3): 42-49.
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    Peck W, Anderson E, Agron J, et al. Hthreads: A computational model for reconfigurable devices[C]// Proceedings of International Conference on Field Programmable Logic and Applications. Madrid, Spain: IEEE Press, 2006: 1-4.
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    Lubbers E, Platzner M. ReconOS: An RTOS supporting hard-and software threads[C]// International Conference on Field Programmable Logic and Applications. Amsterdam, Netherlands: IEEE Press, 2007: 441-446.
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    Vuletic M, Pozzi L, Ienne P. Virtual memory window for application-specific reconfigurable coprocessors[C]// Proceedings of the 41st annual Design Automation Conference. San Diego, USA: ACM Press, 2004: 948-953.
    [12]
    So H K H, Brodersen R. A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH[J]. ACM Transactions on Embedded Computing System, 2008, 7(2): 1-28.
    [13]
    Wang Y, Yan J, Zhou X G, et al. A partially reconfigurable architecture supporting hardware threads[C]// International Conference on Field-Programmable Technology. Seoul, Korea: IEEE Press, 2012: 269-276.
    [14]
    Ismail A, Shannon L. FUSE: Front-end user framework for O/S abstraction of hardware accelerators[C]// IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines. Salt Lake City, USA: IEEE Press, 2011: 170-177.
    [15]
    Gropp W, Lusk E, Skjellum A. Using MPI: Portable Parallel Programming with the Message Passing Interface[M]. Cambridge, USA: MIT press, 1999.
    [16]
    Stratton J A, Stone S S, Hwu W M. MCUDA: An efficient implementation of CUDA kernels for multi-core CPUs[C]// Languages and Compilers for Parallel Computing, Lecture Notes in Computer Science. Berlin, Germany: Springer, 2008, 5335: 16-30.
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    [1]
    Wolf W, Jerraya A A, Martin G. Multiprocessor system-on-chip technology[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2008, 27(10):1 701-1 713.
    [2]
    Compton K, Hauck S. Reconfigurable computing: A survey of systems and software[J]. ACM Computing Surveys, 2002, 34(2): 171-210.
    [3]
    Wang C, Zhang J N, Zhou X H, et al. SOMP: Service-oriented multi processors[C]// IEEE International Conference on Services Computing. Washington, USA: IEEE Computer Society, 2011: 709-716.
    [4]
    Zynq-7000 All Programmable SoC[EB/OL]. http://www.xilinx.com/.
    [5]
    Watkins M A, Albonesi D H. ReMAP: A reconfigurable heterogeneous multicore architecture[C]// 43rd Annual IEEE/ACM International Symposium on Microarchitecture. Atlanta, USA: IEEE Press, 2010: 497-508.
    [6]
    Kahle J A, Day M N, Hofstee H P, et al. Introduction to the Cell multiprocessor[J]. IBM Journal of Research and Development, 2005, 49(4/5): 589-604.
    [7]
    DeHon H, Markovsky Y, Caspi E, et al. Stream computations organized for reconfigurable execution[J]. Microprocessors and Microsystems, 2006, 30(6): 334-354.
    [8]
    Chamberlain R D, Franklin M A, Tyson E J, et al. Auto-pipe: Streaming applications on architecturally diverse systems[J]. Computer, 2010, 43(3): 42-49.
    [9]
    Peck W, Anderson E, Agron J, et al. Hthreads: A computational model for reconfigurable devices[C]// Proceedings of International Conference on Field Programmable Logic and Applications. Madrid, Spain: IEEE Press, 2006: 1-4.
    [10]
    Lubbers E, Platzner M. ReconOS: An RTOS supporting hard-and software threads[C]// International Conference on Field Programmable Logic and Applications. Amsterdam, Netherlands: IEEE Press, 2007: 441-446.
    [11]
    Vuletic M, Pozzi L, Ienne P. Virtual memory window for application-specific reconfigurable coprocessors[C]// Proceedings of the 41st annual Design Automation Conference. San Diego, USA: ACM Press, 2004: 948-953.
    [12]
    So H K H, Brodersen R. A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH[J]. ACM Transactions on Embedded Computing System, 2008, 7(2): 1-28.
    [13]
    Wang Y, Yan J, Zhou X G, et al. A partially reconfigurable architecture supporting hardware threads[C]// International Conference on Field-Programmable Technology. Seoul, Korea: IEEE Press, 2012: 269-276.
    [14]
    Ismail A, Shannon L. FUSE: Front-end user framework for O/S abstraction of hardware accelerators[C]// IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines. Salt Lake City, USA: IEEE Press, 2011: 170-177.
    [15]
    Gropp W, Lusk E, Skjellum A. Using MPI: Portable Parallel Programming with the Message Passing Interface[M]. Cambridge, USA: MIT press, 1999.
    [16]
    Stratton J A, Stone S S, Hwu W M. MCUDA: An efficient implementation of CUDA kernels for multi-core CPUs[C]// Languages and Compilers for Parallel Computing, Lecture Notes in Computer Science. Berlin, Germany: Springer, 2008, 5335: 16-30.
    [17]
    EEMBC benchmark suite[EB/OL]. http://www.eembc.org/, 2009.
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